diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-15 13:09:36 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-02-18 23:21:04 +0000 |
| commit | 520724327088b3fc9d2bd1c25094242982fc1521 (patch) | |
| tree | 2e8d6bb8b5b962f5716128d8d94f8b58d6967ffa | |
| parent | a7e6788ea70ea74fb905ae70035b74ec2caf39fd (diff) | |
soc/intel/common/block/fast_spi: Define __SIMPLE_DEVICE__
Change-Id: Iff6111ab379229daec7a3892c330de6b5f0e5157
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 38 |
1 files changed, 8 insertions, 30 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 7859b53318..e4483e1dac 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <arch/romstage.h> #include <device/mmio.h> #include <assert.h> @@ -20,11 +22,7 @@ */ void *fast_spi_get_bar(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; uintptr_t bar; bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -41,11 +39,7 @@ void *fast_spi_get_bar(void) */ void fast_spi_init(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); @@ -65,11 +59,7 @@ void fast_spi_init(void) */ static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; uint32_t bc_cntl; assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0); @@ -318,11 +308,7 @@ void fast_spi_cache_bios_region(void) */ static void fast_spi_enable_ext_bios(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)) return; @@ -375,11 +361,7 @@ static void fast_spi_enable_ext_bios(void) */ void fast_spi_early_init(uintptr_t spi_base_address) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; uint16_t pcireg; /* Assign Resources to SPI Controller */ @@ -415,11 +397,7 @@ bool fast_spi_wpd_status(void) /* Enable SPI Write Protect. */ void fast_spi_enable_wp(void) { -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_SPI; -#else - struct device *dev = PCH_DEV_SPI; -#endif + const pci_devfn_t dev = PCH_DEV_SPI; uint8_t bios_cntl; bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); |