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authorAaron Durbin <adurbin@chromium.org>2014-11-19 11:57:47 -0600
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 20:44:41 +0200
commit4b0853246f7ec9ae8e89e81c03da7e36c8ce8296 (patch)
tree7b3eb5be124aea4a4d9c069639b55b89b0483782
parentbcea3f64a3fd12f8c068e55108ef3e9a9d46acae (diff)
tegra132: rename clock_display() to clock_configure_plld()
Provide an explicit name for configuring PLLD. The new name, clock_configure_plld(), provides an explicit semantic to what it is doing. Also, provide the printk() about actual frequency vs requested frequency as most of the callers were doing this themselves. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted on ryu. Change-Id: I1880f0f305e69674922b070d282aac3acdc86aad Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c51d5b0864d8bd0db5927380803cec46ccd74d48 Original-Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230773 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-on: http://review.coreboot.org/9524 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/soc/nvidia/tegra132/clock.c11
-rw-r--r--src/soc/nvidia/tegra132/display.c7
-rw-r--r--src/soc/nvidia/tegra132/include/soc/clock.h6
-rw-r--r--src/soc/nvidia/tegra132/tegra_dsi.c2
4 files changed, 14 insertions, 12 deletions
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index 49c2f19dac..661d38a55d 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -291,10 +291,6 @@ static void graphics_pll(void)
/* leave dither and undoc bits set, release clamp */
scfg = (1<<28) | (1<<24);
writel(scfg, cfg);
-
- /* disp1 will be set when panel information (pixel clock) is
- * retrieved (clock_display).
- */
}
/*
@@ -304,8 +300,7 @@ static void graphics_pll(void)
*
* Return the plld frequency if success, otherwise return 0.
*/
-u32
-clock_display(u32 frequency)
+u32 clock_configure_plld(u32 frequency)
{
/**
* plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
@@ -388,6 +383,10 @@ clock_display(u32 frequency)
init_pll(CLK_RST_REG(plld_base), CLK_RST_REG(plld_misc), plld,
(PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE));
+ if (rounded_rate != frequency)
+ printk(BIOS_DEBUG, "PLLD rate: %u vs %u\n", rounded_rate,
+ frequency);
+
return rounded_rate;
}
diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/display.c
index 4fc312ebec..d616b7356f 100644
--- a/src/soc/nvidia/tegra132/display.c
+++ b/src/soc/nvidia/tegra132/display.c
@@ -135,7 +135,8 @@ static int update_display_mode(struct display_controller *disp_ctrl,
* has some requirements to have VCO in range 500MHz~1000MHz (see
* clock.c for more detail). To simplify calculation, we set
* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values
- * may be calculated by clock_display, to allow wider frequency range.
+ * may be calculated by clock_configure_plld(), to allow wider
+ * frequency range.
*
* Note ShiftClockDiv is a 7.1 format value.
*/
@@ -265,12 +266,10 @@ void display_startup(device_t dev)
* update_display_mode() for detail.
*/
/* set default plld */
- plld_rate = clock_display(config->pixel_clock * 2);
+ plld_rate = clock_configure_plld(config->pixel_clock * 2);
if (plld_rate == 0) {
printk(BIOS_ERR, "dc: clock init failed\n");
return;
- } else if (plld_rate != config->pixel_clock * 2) {
- printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate);
}
/* set disp1's clock source to PLLD_OUT0 */
diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index 7fabff74e6..5fadbd0c84 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -378,7 +378,11 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
int clock_get_osc_khz(void);
int clock_get_pll_input_khz(void);
-u32 clock_display(u32 frequency);
+/*
+ * Configure PLLD to requested frequency. Returned value is closest match
+ * within the PLLD's constraints or 0 if an error.
+ */
+u32 clock_configure_plld(u32 frequency);
void clock_early_uart(void);
void clock_external_output(int clk_id);
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
diff --git a/src/soc/nvidia/tegra132/tegra_dsi.c b/src/soc/nvidia/tegra132/tegra_dsi.c
index 3a7949d655..f1e7c9f1c6 100644
--- a/src/soc/nvidia/tegra132/tegra_dsi.c
+++ b/src/soc/nvidia/tegra132/tegra_dsi.c
@@ -463,7 +463,7 @@ static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi,
dsi->slave->clk_rate = dsi->clk_rate;
/* set up plld */
- plld = clock_display(plld);
+ plld = clock_configure_plld(plld);
if (plld == 0) {
printk(BIOS_ERR, "%s: clock init failed\n", __func__);
return -1;