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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2019-06-19 19:46:37 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 09:13:06 +0000
commit493d36684c105d89372598bd4a937e97b2bdf05e (patch)
treef705decd0a23ed7b6b0b542ee66d405ba68e7605
parent09c31d557fb731cac17821e547cdb644ee817463 (diff)
mb/google/hatch/variants/kindred: Update memory strap GPIOs
According to the latest schematic (b:127996858#comment38), MEM_CONFIG_0 --> GPP_H19 MEM_CONFIG_1 --> GPP_H22 MEM_CONFIG_2 --> GPP_F10 MEM_CONFIG_3 --> GPP_F3 BUG=none BRANCH=none TEST=Boot kindred proto board Change-Id: Ib79f9454116583a94fe1fd53a37ed928d32988d5 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
-rw-r--r--src/mainboard/google/hatch/variants/kindred/Makefile.inc3
-rw-r--r--src/mainboard/google/hatch/variants/kindred/gpio.c54
-rw-r--r--src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h8
3 files changed, 61 insertions, 4 deletions
diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc
index 8173ca4389..563275dd19 100644
--- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc
@@ -18,3 +18,6 @@ SPD_SOURCES += 8G_2400 # 0b010
SPD_SOURCES += 8G_2666 # 0b011
SPD_SOURCES += 16G_2400 # 0b100
SPD_SOURCES += 16G_2666 # 0b101
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c
new file mode 100644
index 0000000000..43948a35f8
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/kindred/gpio.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+ /* F3 : MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+ /* F10 : MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+ /* H19 : MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+ /* H22 : MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *override_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+/* GPIOs configured before ramstage */
+static const struct pad_config early_gpio_table[] = {
+ /* F3 : MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
+ /* F10 : MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
+ /* H19 : MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
+ /* H22 : MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
+};
+
+const struct pad_config *override_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h
index 29e590422f..92f9d412fd 100644
--- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h
+++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h
@@ -19,9 +19,9 @@
#include <baseboard/gpio.h>
/* Memory configuration board straps */
-#define GPIO_MEM_CONFIG_0 GPP_F20
-#define GPIO_MEM_CONFIG_1 GPP_F21
-#define GPIO_MEM_CONFIG_2 GPP_F11
-#define GPIO_MEM_CONFIG_3 GPP_F22
+#define GPIO_MEM_CONFIG_0 GPP_H19
+#define GPIO_MEM_CONFIG_1 GPP_H22
+#define GPIO_MEM_CONFIG_2 GPP_F10
+#define GPIO_MEM_CONFIG_3 GPP_F3
#endif