diff options
| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-04-13 13:20:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-16 08:44:50 +0000 |
| commit | 3d34ae3fc4273682de7d9f8e92425af864fd564c (patch) | |
| tree | d14f26858052d938008e3c80655829aafb9c48b1 | |
| parent | bbcfa8afd59b4e31a6ef820e133b3f7353c45b2a (diff) | |
soc/amd/stoneyridge/northbridge.c: Fix bit definitions
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/northbridge.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 92bce98780..365a9f5eef 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -20,6 +20,10 @@ #include <arch/io.h> #include <device/device.h> +/* D1F1 - HDA Configuration Registers */ +#define HDA_DEV_CTRL_STATUS 0x60 +#define HDA_NO_SNOOP_EN BIT(11) + /* D18F0 - HT Configuration Registers */ #define D18F0_NODE_ID 0x60 #define D18F0_CPU_CNT 0x62 /* BKDG defines as a field in DWORD 0x60 */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a7c78e65b0..2cefb9161f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -363,9 +363,9 @@ void fam15_finalize(void *chip_info) /* disable No Snoop */ dev = dev_find_slot(0, HDA0_DEVFN); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); + value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS); + value &= ~HDA_NO_SNOOP_EN; + pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value); } void domain_read_resources(device_t dev) |