diff options
| author | Xiang Wang <wxjstz@126.com> | 2018-07-11 12:13:00 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-18 18:56:10 +0000 |
| commit | 35da319b725805482e4d57571d92cccf65384d63 (patch) | |
| tree | 75d67caf78b3cc8082b884f0ad1410949a85afdf | |
| parent | 3a1a956286d466e0438dc76377db5bdf9fb374ff (diff) | |
riscv: add CAR interface
Add an interface to support cache as ram.
Initialize stack pointer for each hart.
Change-Id: Ic3920e01dd1a7f047a53de57250589000a111409
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/arch/riscv/bootblock.S | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 0b5a2b2961..81a4455d97 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -34,25 +34,26 @@ _start: # csrw mscratch, a1 - # N.B. This only works on low 4G of the address space - # and the stack must be page-aligned. - la sp, _estack - - # poison the stack - la t1, _stack - li t0, 0xdeadbeef - sd t0, 0(t1) + # initialize cache as ram + call cache_as_ram - # make room for HLS and initialize it - addi sp, sp, -HLS_SIZE + # initialize stack point for each hart + # and the stack must be page-aligned. + # 0xDEADBEEF used to check stack overflow + csrr a0, mhartid + la t0, _stack + slli t1, a0, RISCV_PGSHIFT + add t0, t0, t1 + li t1, 0xDEADBEEF + sd t1, 0(t0) + li t1, RISCV_PGSIZE - HLS_SIZE + add sp, t0, t1 - // Once again, the docs and toolchain disagree. - // Rather than get fancy I'll just lock this down - // until it all stabilizes. - //csrr a0, mhartid - csrr a0, 0xf14 + # initialize hart-local storage + csrr a0, mhartid call hls_init + # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 @@ -62,3 +63,8 @@ _start: # set up the mstatus register for VM call mstatus_init tail main + + // These codes need to be implemented on a specific SoC. + .weak cache_as_ram +cache_as_ram: + ret |