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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-03-07 11:15:03 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-10-21 12:29:44 +0000
commit2ac743330c2668abae9eb1d5a01ad1b86ba918a9 (patch)
treef6100eae21855931e8602528b8be6082563e3cbc
parent8fed9d638dcb7ce89880714eb58373205722f749 (diff)
mb/asus/f2a85-m_pro: Enable UART A in Super I/O
Currently, the serial console does not work. With the serial port enabled in the vendor firmware, `superiotool` outputs the global control register values below. Found Nuvoton NCT6779D (id=0xc562) at 0x2e Register dump: idx 10 11 13 14 1a 1b 1c 1d 20 21 22 24 25 26 27 28 2a 2b 2c 2f val ff ff ff ff 3a 28 00 10 c5 62 df 04 00 00 10 00 48 20 00 01 def ff ff 00 00 30 70 10 00 c5 62 ff 04 00 MM 00 00 c0 00 01 MM UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`. This changes the default value 0xc0 to 0x40. Note, due configuring the system as legacy free with `HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in `FchInitResetLpcProgram()`. coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00610f31 APIC 00: ** Enter AmdInitReset [00020007] Fch OEM config in INIT RESET `AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only when coreboot enables the LPC controller again in ramstage, serial output continues. PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 […] done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms Initializing devices... CPU_CLUSTER: 0 init […] Note, due to incorrect Super I/O configuration in the devicetree, the boot hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This will be fixed in follow-up commits. TEST=Receive (some) coreboot log messages over the serial console. Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/asus/f2a85-m/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index 8413cd3863..27d5517b9f 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO
+ select SUPERIO_NUVOTON_COMMON_COM_A if BOARD_ASUS_F2A85_M_PRO
select BOARD_ROMSIZE_KB_8192
select GFXUMA