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authorArthur Heymans <arthur@aheymans.xyz>2019-10-20 14:24:57 +0200
committerNico Huber <nico.h@gmx.de>2019-11-05 09:40:44 +0000
commit127b820d243523fceefb4c5470a5050aa3666dfd (patch)
tree44048dcc2f76c3785c8366b2de65b17ec9d47f27
parent1e07d40027b65e7c5aa0926146f826e7038f7e4e (diff)
soc/intel/common: Don't link CAR teardown in romstage
This is done in postcar stage. This also assumes CAR tear down will always be done in postcar stage. Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/common/block/cpu/Makefile.inc1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc
index f263053430..323d15739c 100644
--- a/src/soc/intel/common/block/cpu/Makefile.inc
+++ b/src/soc/intel/common/block/cpu/Makefile.inc
@@ -3,7 +3,6 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_r
bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S
bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
-romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S