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authorNico Huber <nico.huber@secunet.com>2013-05-14 11:02:43 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-05-22 17:59:10 +0200
commit0da92863a754828eb807f1a15927f0dc288a1788 (patch)
tree65d6c31ee5f7989fd82633c3743e5d8c8f525c42
parent0f43af2ebb0d34ef6106d39d8614590253d5f4a9 (diff)
intel/gm45: Fix interpretation of VT-d disable bit
When configuring the GTT size for the integrated graphics, the state of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is _disabled_. In the log of a VT-d enabled roda/rk9 we have now: [...] VT-d enabled [...] IGD decoded, subtracting 32M UMA and 4M GTT [...] Without this patch, only 2M GTT were reported. Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3252 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/northbridge/intel/gm45/igd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index d54ee41f83..0a8f21e586 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -67,7 +67,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
reg16 = pci_read_config16(mch_dev, D0F0_GGC);
reg16 &= 0xf00f;
reg16 |= 0x0350;
- if (capid & (1 << (48 - 32)))
+ if (!(capid & (1 << (48 - 32))))
reg16 |= 0x0800;
pci_write_config16(mch_dev, D0F0_GGC, reg16);