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authorRonald G. Minnich <rminnich@gmail.com>2006-05-04 23:05:49 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-05-04 23:05:49 +0000
commit070a10f7593014f1ae8a0f15d34293f59790f9cf (patch)
tree5b7d4036350d6ed6ebff5ca987e966a9a35f7d82
parentab4f5d0c10b23021608eaec56836a7d063837f3f (diff)
mods for early printing on OLPC
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/include/cpu/amd/gx2def.h5
-rw-r--r--src/southbridge/amd/cs5536/cs5536_early_setup.c59
-rw-r--r--targets/olpc/rev_a/Config.lb25
3 files changed, 74 insertions, 15 deletions
diff --git a/src/include/cpu/amd/gx2def.h b/src/include/cpu/amd/gx2def.h
index 0c636ef2b5..074e36110b 100644
--- a/src/include/cpu/amd/gx2def.h
+++ b/src/include/cpu/amd/gx2def.h
@@ -89,7 +89,8 @@
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1)
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1)
/* South Bridge*/
-#define MSR_SB (SB_PORT << 23) + MSR_PCI /* address to the SouthBridge*/
+#define SB_PORT 2 /* port of the SouthBridge */
+#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* address to the SouthBridge*/
#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
@@ -502,7 +503,7 @@
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
#define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1
-#define SB_PORT 2 // port of the SouthBridge
+
/* standard AMD post definitions -- might as well use them. */
#define POST_Output_Port (0x080) /* port to write post codes to*/
diff --git a/src/southbridge/amd/cs5536/cs5536_early_setup.c b/src/southbridge/amd/cs5536/cs5536_early_setup.c
index eb8f9f5140..bf77087a47 100644
--- a/src/southbridge/amd/cs5536/cs5536_early_setup.c
+++ b/src/southbridge/amd/cs5536/cs5536_early_setup.c
@@ -113,6 +113,24 @@ static void cs5536_setup_gpio(void)
//outl(0x3ffbc004, 0x6100 + 0x34);
outl(0x3fffc000, 0x6100 + 0x34);
//outl(val, 0x6100 + 0x34);
+
+#if 0
+ /* changes proposed by Ollie; we will test this later. */
+ /* setup GPIO pins 14/15 for SDA/SCL */
+ val = GPIOL_15_SET | GPIOL_14_SET;
+ /* Output Enable */
+ //outl(0x3fffc000, 0x6100 + 0x04);
+ outl(val, 0x6100 + 0x04);
+ /* Output AUX1 */
+ //outl(0x3fffc000, 0x6100 + 0x10);
+ outl(val, 0x6100 + 0x10);
+ /* Input Enable */
+ //outl(0x3fffc000, 0x6100 + 0x20);
+ outl(val, 0x6100 + 0x20);
+ /* Input AUX1 */
+ //outl(0x3fffc000, 0x6100 + 0x34);
+ outl(val, 0x6100 + 0x34);
+#endif
}
static void cs5536_disable_internal_uart(void)
@@ -158,7 +176,8 @@ static void dummy(void)
/* see page 412 of the cs5536 companion book */
static int cs5536_setup_onchipuart(void)
{
- /* ToDo:
+ unsigned long m;
+ /*
* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
* 2. Enable UART IO space in MDD
@@ -171,8 +190,46 @@ static int cs5536_setup_onchipuart(void)
msr_t msr;
msr.lo = 2;
msr.hi = 0;
+ /* not sure what this is for, so comment it out ...
wrmsr(0x5140003a, msr);
wrmsr(0x5140003e, msr);
+ */
+
+
+ /* GPIO8 - UART1_TX */
+ /* Set: Output Enable (0x4) */
+ m = inl(GPIOL_OUTPUT_ENABLE);
+ m |= GPIOL_8_SET;
+ m &= ~GPIOL_8_CLEAR;
+ outl(m,GPIOL_OUTPUT_ENABLE);
+ /* Set: OUTAUX1 Select (0x10) */
+ m = inl(GPIOL_OUT_AUX1_SELECT);
+ m |= GPIOL_8_SET;
+ m &= ~GPIOL_8_CLEAR;
+ outl(m,GPIOL_OUT_AUX1_SELECT);
+ /* Set: Pull Up (0x18) */
+ m = inl(GPIOL_PULLUP_ENABLE);
+ m |= GPIOL_8_SET;
+ m &= ~GPIOL_8_CLEAR;
+ /* GPIO9 - UART1_RX */
+ /* Set: Pull Up (0x18) */
+ m |= GPIOL_9_SET;
+ m &= ~GPIOL_9_CLEAR;
+ outl(m,GPIOL_PULLUP_ENABLE);
+ /* Set: Input Enable (0x20) */
+ m = inl(GPIOL_INPUT_ENABLE);
+ m |= GPIOL_9_SET;
+ m &= ~GPIOL_9_CLEAR;
+ outl(m,GPIOL_INPUT_ENABLE);
+ /* Set: INAUX1 Select (0x34) */
+ m = inl(GPIOL_IN_AUX1_SELECT);
+ m |= GPIOL_9_SET;
+ m &= ~GPIOL_9_CLEAR;
+ outl(m,GPIOL_IN_AUX1_SELECT);
+
+ msr = rdmsr(MDD_LEG_IO);
+ msr.lo |= 0x7 << 16;
+ wrmsr(MDD_LEG_IO,msr);
}
static int cs5536_early_setup(void)
diff --git a/targets/olpc/rev_a/Config.lb b/targets/olpc/rev_a/Config.lb
index 703d4b7bc4..3d68559a45 100644
--- a/targets/olpc/rev_a/Config.lb
+++ b/targets/olpc/rev_a/Config.lb
@@ -5,17 +5,17 @@ mainboard olpc/rev_a
option ROM_SIZE=1024*256
-romimage "normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_IMAGE_SIZE=0x10000
- option LINUXBIOS_EXTRA_VERSION=".0Normal"
-# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
-# payload ../../../../tg3--ide_disk.zelf
-# payload ../../../../../lnxieepro100.ebi
-# payload /etc/hosts
-# payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
- payload /tmp/filo.elf
-end
+#romimage "normal"
+# option USE_FALLBACK_IMAGE=0
+# option ROM_IMAGE_SIZE=0x10000
+# option LINUXBIOS_EXTRA_VERSION=".0Normal"
+## payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
+## payload ../../../../tg3--ide_disk.zelf
+## payload ../../../../../lnxieepro100.ebi
+## payload /etc/hosts
+## payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
+# payload /tmp/filo.elf
+#end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
@@ -29,4 +29,5 @@ romimage "fallback"
payload /tmp/filo.elf
end
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+buildrom ./linuxbios.rom ROM_SIZE "fallback"
+#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"