diff options
| author | Zhanyong Wang <zhanyong.wang@mediatek.com> | 2020-05-14 13:27:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:55:53 +0000 |
| commit | 06639f2abf86bd0eef9c7808b7e724450d1408b8 (patch) | |
| tree | 26201f0c284e772f312dcb55f0e4ea04490fecea | |
| parent | 5acea15d63e821a1bc416d206162ed030cd5d57c (diff) | |
soc/mediatek/mt8192: Refactor USB code among similar SoCs
Adjust ssusb register layout and offset accroding mt8192 Soc
then refactor USB code which will be reused among similar SoCs
Signed-off-by: Tianping Fang <tianping.fang@mediatek.com>
Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
| -rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/usb.h | 24 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/usb.c | 15 |
3 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index c7dbe51b22..533eae294d 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c +ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h new file mode 100644 index 0000000000..c988270e4b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/usb.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_USB_H +#define SOC_MEDIATEK_MT8192_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 2 + +#endif diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c new file mode 100644 index 0000000000..44f2f150ed --- /dev/null +++ b/src/soc/mediatek/mt8192/usb.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <device/mmio.h> +#include <soc/usb.h> + +#define REG_SPM_POWERON_CONFIG_EN (void *)(SPM_BASE + 0x000) +#define REG_SPM_SSPM_PWR_CON (void *)(SPM_BASE + 0x390) + +void mtk_usb_prepare(void) +{ + /* power on SSUSB SRAM FIFO */ + setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); + clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); +} |