diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2020-09-17 11:49:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-30 10:16:05 +0000 |
| commit | 05ea79cf53f8c425b688c322f750acdfb428198a (patch) | |
| tree | d5960f4b0f4f024de0072b8643fe81e7c240a0d9 | |
| parent | 3554888f25d860cad53a0f2e5439b4fc884578ef (diff) | |
soc/intel/tigerlake: Set TME upd param based on config
Set TmeEnable FSP-M upd based on config.
TEST: TME ENABLE and LOCK bits get set when Tme is enabled.
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 39572997c3..dc9caee9fb 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -211,6 +211,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |