diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-02-15 21:42:38 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-18 22:47:59 +0000 |
| commit | 02bec2bd5cbef9ab5fab422b801768686e436b51 (patch) | |
| tree | c8124d89ed68afce6064e4becca8673babef1253 | |
| parent | c867cd36759253f418d2b2e2475276cbac52c370 (diff) | |
lib: Add DDR5 DRAM type
TEST=Not seeing default msg "Defaulting to using DDR4 params." with
this CL.
Change-Id: Ib751396ec74b1491fd08b88b07462b315c4a152d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/lib/spd_bin.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 863218c2d3..213d5f4561 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -33,6 +33,7 @@ static bool use_ddr4_params(int dram_type) /* Below DDR type share the same attributes */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: + case SPD_DRAM_DDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: return true; @@ -163,6 +164,7 @@ static void spd_get_name(const uint8_t spd[], int type, const char **spd_name, s /* LPDDR3, LPDDR4 and DDR4 have same part number offset and length */ case SPD_DRAM_LPDDR3_JEDEC: case SPD_DRAM_DDR4: + case SPD_DRAM_DDR5: case SPD_DRAM_LPDDR4: case SPD_DRAM_LPDDR4X: *spd_name = (const char *) &spd[DDR4_SPD_PART_OFF]; |