diff options
| author | Ryan Salsamendi <rsalsamendi@hotmail.com> | 2017-06-30 17:29:37 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-07-03 10:33:16 +0000 |
| commit | fa0725dead0fdc7e9330e77c42ff4ed4b36a89c4 (patch) | |
| tree | 95f4af78e21bf1e8a07ab6d27d0224206721c406 | |
| parent | 889ce9c91ecabb40f079111b22124560c55be4e6 (diff) | |
northbridge/intel/haswell: Fix undefined behavior
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/drivers/intel/gma/i915_reg.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 12 |
3 files changed, 13 insertions, 7 deletions
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index dee6865224..e88ecfb87e 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -2979,7 +2979,7 @@ /* Ironlake */ #define CPU_VGACNTRL 0x41000 -#define CPU_VGA_DISABLE (1<<31) +#define CPU_VGA_DISABLE (1UL<<31) #define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -4177,7 +4177,7 @@ #define HSW_PWR_WELL_CTL2 0x45404 /* Driver */ #define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */ #define HSW_PWR_WELL_CTL4 0x4540C /* Debug */ -#define HSW_PWR_WELL_ENABLE (1<<31) +#define HSW_PWR_WELL_ENABLE (1UL<<31) #define HSW_PWR_WELL_STATE (1<<30) #define HSW_PWR_WELL_CTL5 0x45410 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f22ff48707..75f3b7a944 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -252,13 +252,13 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write_regs(haswell_gt_setup); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + gtt_poll(0x138124, (1UL << 31), (0UL << 31)); /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); /* Mailbox Command */ gtt_write(0x138124, 0x80000004); /* Wait for Mailbox Ready */ - gtt_poll(0x138124, (1 << 31), (0 << 31)); + gtt_poll(0x138124, (1UL << 31), (0UL << 31)); /* Enable PM Interrupts */ gtt_write(GEN6_PMIER, GEN6_PM_MBOX_EVENT | GEN6_PM_THERMAL_EVENT | diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a8c8015d97..32be916a45 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -36,6 +36,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; + u32 mask; *base = 0; *len = 0; @@ -47,15 +48,20 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; case 1: // 128M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask |= (1 << 27); + *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; case 2: // 64M - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); + mask |= (1 << 27) | (1 << 26); + *base = pciexbar_reg & mask; *len = 64 * 1024 * 1024; return 1; } |