diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-10-29 21:44:29 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:50:24 +0000 |
commit | f578b6f8f4374597cea5ce887c80216b5f7eccb9 (patch) | |
tree | 829ba2b7b42e80b5f631bde9e9f463b08306976f | |
parent | 849104f2fb32188185d276ba68166a6537ed69c9 (diff) |
nb/intel/haswell: Calculate TSEG limit from registers
Done for consistency with other northbridges.
Change-Id: I08023809477c1cef0d7762b5e4fde65fadf6a6d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 02d120b119..c19cfecc73 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -4,13 +4,13 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci_ops.h> #include <cbmem.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt_register.h> +#include <types.h> #include "haswell.h" @@ -19,9 +19,9 @@ static uintptr_t northbridge_get_tseg_base(void) return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, TSEG), 1 * MiB); } -static size_t northbridge_get_tseg_size(void) +static uintptr_t northbridge_get_tseg_limit(void) { - return CONFIG_SMM_TSEG_SIZE; + return ALIGN_DOWN(pci_read_config32(HOST_BRIDGE, BGSM), 1 * MiB); } union dpr_register txt_get_chipset_dpr(void) @@ -62,7 +62,9 @@ void *cbmem_top_chipset(void) void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); - *size = northbridge_get_tseg_size(); + *size = northbridge_get_tseg_limit(); + + *size -= *start; } void fill_postcar_frame(struct postcar_frame *pcf) |