diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-12-22 13:42:39 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-24 08:15:51 +0000 |
| commit | f0df12dd176a6e83645116cfc852d4753e3f234d (patch) | |
| tree | 030d28d8e513b64d9eb8b7a951a5f15450cb5814 | |
| parent | 749a78d1794661cfbd72121484eb2b9b80361af8 (diff) | |
mb/google/volteer/var/voema: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:169356808
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/voema/overridetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 9efcdb22f3..8d05c3213f 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -81,6 +81,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. |