diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2020-09-22 17:15:49 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-10-05 18:02:51 +0000 |
| commit | edecf46187a9efd626bbcf15b4dc71cede027861 (patch) | |
| tree | bcc804459070387c0b0bf49a9082d64f69c53a5c | |
| parent | 3b24bb6fc8c2a8b672775b70d020a1a8aa87b8e0 (diff) | |
vendorcode/google: add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option to declare whether
the SPD Module Part Number (memory part name) is stored in the CBI.
Move mainboard_get_dram_part_num() into src/vendor/google/chromeos
to allow mainboards to use it without having to duplicate that code
by enabling the CHROMEOS_DRAM_PART_NUMBER_IN_CBI config option.
BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot && emerge-nocturne coreboot" and verify it
builds.
Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/vendorcode/google/chromeos/Kconfig | 7 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/vendorcode/google/chromeos/dram_part_num_override.c | 31 |
3 files changed, 40 insertions, 0 deletions
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 0528d00fea..9ed24a9924 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -103,5 +103,12 @@ config CHROMEOS_CSE_BOARD_RESET_OVERRIDE does not understand the new cr50 strap config (applicable only to boards using strap config 0xe). Enabling this config will help to override the default global reset. +config CHROMEOS_DRAM_PART_NUMBER_IN_CBI + def_bool n + depends on EC_GOOGLE_CHROMEEC + help + Some boards declare the DRAM part number in the CBI instead of the SPD. This option + allows those boards to declare that their DRAM part number is stored in the CBI. + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17236d9d2..fb11e11c8d 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -16,3 +16,5 @@ bootblock-y += watchdog.c verstage-y += watchdog.c romstage-y += watchdog.c ramstage-y += watchdog.c + +romstage-$(CONFIG_CHROMEOS_DRAM_PART_NUMBER_IN_CBI) += dram_part_num_override.c diff --git a/src/vendorcode/google/chromeos/dram_part_num_override.c b/src/vendorcode/google/chromeos/dram_part_num_override.c new file mode 100644 index 0000000000..d624e13c7e --- /dev/null +++ b/src/vendorcode/google/chromeos/dram_part_num_override.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <memory_info.h> + +const char *mainboard_get_dram_part_num(void) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + static enum { + PART_NUM_NOT_READ, + PART_NUM_AVAILABLE, + PART_NUM_NOT_IN_CBI, + } part_num_state = PART_NUM_NOT_READ; + + if (part_num_state == PART_NUM_NOT_READ) { + if (google_chromeec_cbi_get_dram_part_num(part_num_store, + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, + "ERROR: Couldn't obtain DRAM part number from CBI\n"); + part_num_state = PART_NUM_NOT_IN_CBI; + } else { + part_num_state = PART_NUM_AVAILABLE; + } + } + + if (part_num_state == PART_NUM_NOT_IN_CBI) + return NULL; + + return part_num_store; +} |