diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-03-11 16:01:20 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-03-12 04:23:58 +0000 |
| commit | ebac8c772f81e4b596778a3027eeb27d6dc59f0a (patch) | |
| tree | cf5556b4da87dd6e593589733306c149ac1d3994 | |
| parent | 52331ba4f7f08ea3c27d5d7c87b4078dea14c42d (diff) | |
Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI
Some new feature added into FSP specification to perform dispatching
of external PPI service from boot firmware (coreboot) to FSP.
Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 4 | ||||
| -rw-r--r-- | Documentation/soc/intel/fsp/ppi/ppi.md | 9 |
2 files changed, 13 insertions, 0 deletions
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 039a389b46..d7f44c6dee 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -11,3 +11,7 @@ This section contains documentation about Intel-FSP in public domain. * [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf) * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf) + +## Additional Features in FSP 2.1 specification + +- [PPI](ppi/ppi.md) diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md new file mode 100644 index 0000000000..66dbf07c16 --- /dev/null +++ b/Documentation/soc/intel/fsp/ppi/ppi.md @@ -0,0 +1,9 @@ +# PEIM to PEIM Interface (PPI) + +This section is intended to document the purpose of creating PPI service +inside coreboot space to perform some specific operation related to CPU, +chipset using Intel FSP. This feature is added into FSP specification 2.1 +where FSP should be able to locate PPI, published by boot firmware and +able to execute the same in FSP's context. + +* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf) |