diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2019-04-15 15:29:26 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-07 21:04:21 +0000 |
| commit | eb5e47dd9467602d09a3f8e6e4cf5dd702bb0cc4 (patch) | |
| tree | 600bfaccdca047a7b04aaaa846fc0b7fa7af6d12 | |
| parent | 142258c2f6cbfd76caf749395e666de0b0595318 (diff) | |
mediatek/mt8183: update dcxo output buffer setting
DCXO consists of core that generates clock and output buffers that
provide clock to other peripheral components.
This patch mainly eliminates the extra power consumption of output buffers.
We only enable the buffer for SOC and disable unused buffers for power-saving.
Also disable useless buffer power mode to guarantee the lowest power state.
BRANCH=none
TEST=Boots correctly on Kukui.
Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32323
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/rtc.h | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8183/rtc.c | 5 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 841a202519..1f6f06a568 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -147,6 +147,7 @@ enum { PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 5879088434..3bd3ab4921 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -274,9 +274,10 @@ static void dcxo_init(void) rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); |