diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-07-02 11:03:44 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-03 15:35:44 +0000 |
| commit | d3758540a951510ede21ebb76cbc196ae8ed0e68 (patch) | |
| tree | 0365a46074796f97c72cfb58a83d691ea64b8e07 | |
| parent | b798deb1d5cf6f5015a224a119a6241b45f36873 (diff) | |
soc/amd/common: fix eSPI virtual wire polarity encoding
eSPI interrupts are active level high. The eSPI polarity register
in the chipset inverts incoming signals if the corresonding bit
is 0 in the register. Therefore, all active high (edge or level)
virtual wire interrupts need to ensure they are not inverted.
And really the sender of the interrupts should be conforming to the
the eSPI spec. As such inverting any signals should not be necessary,
but this register in the chipset allows for fixing up those misbehaviors.
BUG=b:157984427
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/espi.h | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index e882af0305..2bfef890cc 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -43,14 +43,11 @@ #define ESPI_OOB_CH_EN (1 << 1) #define ESPI_FLASH_CH_EN (1 << 0) -/* - * Virtual wire interrupt polarity. If the interrupt is active level high or active falling - * edge, then controller expects its bit to be cleared in ESPI_RXVW_POLARITY whereas if the - * interrupt is active level low or active rising edge, then its bit needs to be set in - * ESPI_RXVW_POLARITY. - */ -#define ESPI_VW_IRQ_LEVEL_HIGH(x) (0 << (x)) -#define ESPI_VW_IRQ_LEVEL_LOW(x) (1 << (x)) +/* Virtual wire interrupt polarity. eSPI interrupts are active level high signals. The + polarity register inverts the incoming signal if the associated bit with the irq is + 0. */ +#define ESPI_VW_IRQ_LEVEL_HIGH(x) (1 << (x)) +#define ESPI_VW_IRQ_LEVEL_LOW(x) (0 << (x)) #define ESPI_VW_IRQ_EDGE_HIGH(x) (1 << (x)) #define ESPI_VW_IRQ_EDGE_LOW(x) (0 << (x)) |