diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2013-02-10 21:20:39 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-02-11 08:24:02 +0100 |
| commit | c52e1065df07c24606381efb7598b1d29dc625b1 (patch) | |
| tree | 7a1dc76e2b4c828207868f99fed58cce23c40661 | |
| parent | e07e253bc87d6a86e5fb7f62bb63438ae4f6c5ba (diff) | |
AMD S3: Add missing erasing flash sector for saving MTRR register
It has worked up to now because the region is already erased
the first time the board boots, and every additional boot the
same data is being written over the old data.(by Dave Frodin)
Change-Id: Id334c60668e31d23c1d552d0ace8eb6ae5513e6b
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2304
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
| -rw-r--r-- | src/cpu/amd/agesa/s3_resume.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 7069c77f1a..5b4c2c3d42 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -168,6 +168,8 @@ void OemAgesaSaveMtrr(void) flash->spi->rw = SPI_WRITE_FLAG; spi_claim_bus(flash->spi); + flash->erase(flash, S3_DATA_MTRR_POS, S3_DATA_MTRR_SIZE); + /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; |