diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 23:48:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-04 00:10:20 +0000 |
| commit | c0dbd4cb562b6c2d569eeb12562bfa3eb27925c9 (patch) | |
| tree | 711de2ed198e253a2106ea5020b11a64b21e164e | |
| parent | 404aea866ce60af9f8756f0698dcd8293c0e81bf (diff) | |
soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index d45c3b04a7..60fd6f9686 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -75,6 +75,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 #define GPP_CLK0_REQ_SHIFT 0 @@ -135,10 +139,6 @@ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ -#define PM1_LIMIT 16 -#define GPE0_LIMIT 28 -#define TOTAL_BITS(a) (8 * sizeof(a)) - /* SATA Controller D11F0 */ #define SATA_MISC_CONTROL_REG 0x40 #define SATA_MISC_SUBCLASS_WREN BIT(0) |