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authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-09-06 11:37:46 -0600
committerMartin Roth <martinroth@google.com>2017-09-26 16:42:38 +0000
commitbbf91af9a22ad375e424c40e12f6807fcaf6965c (patch)
tree6e82543a756a29ac7d1ee419cc745827769261ce
parent29f1b747954784a7b133e9db79382d8d466a7f3a (diff)
amd/stoneyridge: Remove EXT_CONF_SUPPORT check
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC. Clean up northbridge.c by removing the check for the config value set. Remove the CPU initialization code that clears the EnableCf8ExtCfg bit. The location where it was set was removed in c1d72942 Disable PCI_CFG_EXT_IO BUG=b:66202622 Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21497 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/amd/stoneyridge/model_15_init.c5
-rw-r--r--src/soc/amd/stoneyridge/northbridge.c4
2 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c
index 7dfcdb81f1..e89671821d 100644
--- a/src/soc/amd/stoneyridge/model_15_init.c
+++ b/src/soc/amd/stoneyridge/model_15_init.c
@@ -71,11 +71,6 @@ static void model_15_init(device_t dev)
/* Enable the local CPU APICs */
setup_lapic();
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 922342971c..16cda01cf2 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -44,10 +44,6 @@
#include <Porting.h>
#include <Topology.h>
-#if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
-#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
-#endif
-
typedef struct dram_base_mask {
u32 base; /* [47:27] at [28:8] */
u32 mask; /* [47:27] at [28:8] and enable at bit 0 */