diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-01 17:33:42 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-08 13:49:45 +0000 |
| commit | b4b9efcfdd47efe67b13e1cf8cfea2ffe08fb012 (patch) | |
| tree | e701ef4e442478ab8ce9457f126c0d1a016e07f4 | |
| parent | b435d4405dacdc218777aaba349151ae28997741 (diff) | |
soc/amd/stoneyridge: Finish read/write misc registers
Add 16 and 32-bit versions of read / write_misc functions. Find one
access of the MISC block still using read8() and write8(), and convert
it.
Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/sb_util.c | 20 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 6 |
3 files changed, 26 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 098d24edbb..e5ba2af5eb 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -503,7 +503,11 @@ u32 acpi_read32(u8 reg); void acpi_write8(u8 reg, u8 value); void acpi_write16(u8 reg, u16 value); void acpi_write32(u8 reg, u32 value); +u8 misc_read8(u8 reg); +u16 misc_read16(u8 reg); u32 misc_read32(u8 reg); +void misc_write8(u8 reg, u8 value); +void misc_write16(u8 reg, u16 value); void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); uint16_t smi_read16(uint8_t offset); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 530e9cd946..5aec431593 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -219,11 +219,31 @@ void smbus_write16(u8 reg, u16 value) /* misc read/write - access registers at 0xfed80e00 */ +u8 misc_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + u32 misc_read32(u8 reg) { return read32((void *)(ACPIMMIO_MISC_BASE + reg)); } +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + void misc_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_MISC_BASE + reg), value); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7dc27c86da..b5901782f6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -391,14 +391,12 @@ static void sb_enable_legacy_io(void) void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; - u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(ACPIMMIO_MISC_BASE - + MISC_CLK_CNTL1); /* * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. */ - ctrl = read32(misc_clk_cntl_1_ptr); + ctrl = misc_read32(MISC_CLK_CNTL1); switch (osc) { case 1: @@ -410,7 +408,7 @@ void sb_clk_output_48Mhz(u32 osc) default: return; /* do nothing if invalid */ } - write32(misc_clk_cntl_1_ptr, ctrl); + misc_write32(MISC_CLK_CNTL1, ctrl); } static uintptr_t sb_spibase(void) |