diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2021-01-08 09:52:02 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-11 07:35:27 +0000 |
| commit | b3e5c2371db9c263dc64a2955ae4800b6124ce83 (patch) | |
| tree | 1f7794dc969021a99ab9056aff2e4b65ce0788e6 | |
| parent | 82e111cc2a8795cefca36e57031d3d2da0f919aa (diff) | |
vendorcode/intel/fsp: Update Tiger Lake v3444 FSP Headers
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 28 |
1 files changed, 20 insertions, 8 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 276ac79c4c..e791115c26 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -931,7 +931,17 @@ typedef struct { /** Offset 0x04BA - Reserved **/ - UINT8 Reserved20[7]; + UINT8 Reserved20[2]; + +/** Offset 0x04BC - Disable TC code On USB Connect + Enable(default) or Disable TC cold On Usb Connected + $EN_DIS +**/ + UINT8 DisableTccoldOnUsbConnected; + +/** Offset 0x04BD - Reserved +**/ + UINT8 Reserved21[4]; /** Offset 0x04C1 - Enable VMD controller Enable/disable to VMD controller.0: Disable(Default); 1: Enable @@ -965,7 +975,7 @@ typedef struct { /** Offset 0x04C6 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; /** Offset 0x04C7 - VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) @@ -975,7 +985,7 @@ typedef struct { /** Offset 0x04C8 - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved23; /** Offset 0x04C9 - VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH @@ -985,7 +995,7 @@ typedef struct { /** Offset 0x04CA - Reserved **/ - UINT8 Reserved23; + UINT8 Reserved24; /** Offset 0x04CB - VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH @@ -1001,7 +1011,7 @@ typedef struct { /** Offset 0x04CD - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved25; /** Offset 0x04CE - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides @@ -1048,9 +1058,11 @@ typedef struct { **/ UINT8 VccSt; -/** Offset 0x04DD - Reserved +/** Offset 0x04DD - TCSS Usb3 Compliance Mode Enable + Used by IOM FW to skip powering down the PHY at the end of disconnect flow + $EN_DIS **/ - UINT8 Reserved25; + UINT8 Usb3ComplModeEnable; /** Offset 0x04DE - ITBT DMA LTR TCSS DMA1, DMA2 LTR value |