diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2016-03-14 17:38:51 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-11 17:57:55 +0200 |
| commit | b13d454f35a00e4515e4eae0b3d22255db8a034f (patch) | |
| tree | b05969c2a63251f9be6c83c6f3c878b18c2bbf94 | |
| parent | 064a50160a55058a7baa00a91cbb9ceb0126cda6 (diff) | |
soc/intel/apollolake: Enable CACHE_MRC_SETTINGS
This enables CACHE_MRC_SETTINGS by default as well selects
timer configuration.
Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14252
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 1 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 30ee7e57a1..10e8b0d294 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -35,8 +35,8 @@ config CPU_SPECIFIC_OPTIONS select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE - select UDELAY_TSC - select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select HAVE_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 config MMCONF_BASE_ADDRESS @@ -100,4 +100,8 @@ config ROMSTAGE_ADDR help The base address (in CAR) where romstage should be linked +config CACHE_MRC_SETTINGS + bool + default y + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index eb3058dec1..dff1589cdb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -44,6 +44,7 @@ postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +postcar-y += tsc_freq.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include |