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authorMatt DeVillier <matt.devillier@gmail.com>2016-10-28 00:37:16 -0500
committerMartin Roth <martinroth@google.com>2017-06-16 16:09:57 +0200
commitaff9b308510b799f975d4c369777bafa1c4fdead (patch)
tree510ab617ca5ba65307d9c862ed5020eecb125ce4
parent739ded5c182917083975230bea7d125e87923a85 (diff)
southbridge/bd82x6x - add GNVS var for trackpad IRQ
Add a GNVS variable to store trackpad IRQ for google/parrot, so that both SNB and IVB variants can be built with the same config Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/20092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl1
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h3
2 files changed, 3 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index ad027160a6..2a3227d3da 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -175,6 +175,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
ALFP, 8, // 0xf2 - active lfp
IMON, 8, // 0xf3 - current graphics turbo imon value
MMIO, 8, // 0xf4 - 64bit mmio support
+ TPIQ, 8, // 0xf5 - trackpad IRQ value
/* ChromeOS specific */
Offset (0x100),
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 8775335c3e..e71fedae91 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -145,7 +145,8 @@ typedef struct {
u8 alfp; /* 0xf2 - active lfp */
u8 imon; /* 0xf3 - current graphics turbo imon value */
u8 mmio; /* 0xf4 - 64bit mmio support */
- u8 rsvd13[11]; /* 0xf5 - rsvd */
+ u8 tpiq; /* 0xf5 - trackpad IRQ value */
+ u8 rsvd13[10]; /* 0xf6 - rsvd */
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;