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authorDavid Hendricks <dhendrix@chromium.org>2013-04-22 16:03:11 -0700
committerDavid Hendricks <dhendrix@chromium.org>2013-04-23 03:20:44 +0200
commitaee444f453f38e53f3e2ac54b560707616767869 (patch)
treec504f2853a7d0779258abae395c7663ebfdf2b0f
parente8a91347b182281f18c969229f02e07102e21898 (diff)
exynos5250: ungate the product ID register
This makes sure that the product ID (PRO_ID) register can be read when the OS kernel is figuring out what kind of CPU it's running on. For historical reference, the original U-Boot code seems to have worked basically by accident here. The hardware has a quirk where by reading the value before gating the IP block keeps the value persistent. U-Boot reads the chip ID early on to distinguish between chip family, but we do not mix code the same way so we do not read the chip ID. Since the value has been read before the clock gating happens, the value remains available for the kernel to use during the decompression stage. We don't want to rely on that behavior when using coreboot. Instead the kernel should gate unused IPs. (credit to Gabe for finding symptom in the kernel) Change-Id: Iaa21e6e718b9000b5558f568020f393779fd208e Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3121 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
-rw-r--r--src/cpu/samsung/exynos5250/clock_init.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index c94cadfbd4..0989b88bb5 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -416,7 +416,12 @@ void clock_gate(void)
CLK_SPI2_MASK |
CLK_SPI0_MASK);
- /* CLK_GATE_IP_PERIS */
+ /*
+ * CLK_GATE_IP_PERIS
+ * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID
+ * register (PRO_ID) works correctly when the OS kernel determines
+ * which chip it is running on.
+ */
clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK |
CLK_TZPC9_MASK |
CLK_TZPC8_MASK |
@@ -427,8 +432,7 @@ void clock_gate(void)
CLK_TZPC3_MASK |
CLK_TZPC2_MASK |
CLK_TZPC1_MASK |
- CLK_TZPC0_MASK |
- CLK_CHIPID_MASK);
+ CLK_TZPC0_MASK);
/* CLK_GATE_BLOCK */
clrbits_le32(&clk->gate_block, CLK_ACP_MASK);