vendorcode/amd/agesa: Sync irrelevant differences

After modifications:

  f12 and f14 are identical
  f10 is f14 with invd -> wbinvd modification added to HOOK_F10
  f15 is f10 with invd -> wbinvd modification added to HOOK_F15
  f15tn is f15 modified to use with TN / KV / KM

Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

6 files changed, 54 insertions, 4 deletions

diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index b89834fc21..88fa79d2ea 100644
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -42,7 +42,12 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
+#ifdef __x86_64__
+CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
+#else
 CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */
+#endif
 
 APIC_BASE_ADDRESS       =       0x0000001B
   APIC_BSC              =       8               /* Boot Strap Core  */
@@ -61,6 +66,20 @@ AMD_MTRR_FIX4k_E8000     =      0x026D
 AMD_MTRR_FIX4k_F0000     =      0x026E
 AMD_MTRR_FIX4k_F8000     =      0x026F
 
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000  =  0x00000250
+AMD_AP_MTRR_FIX16k_80000  =  0x00000258
+AMD_AP_MTRR_FIX16k_A0000  =  0x00000259
+AMD_AP_MTRR_FIX4k_C0000   =  0x00000268
+AMD_AP_MTRR_FIX4k_C8000   =  0x00000269
+AMD_AP_MTRR_FIX4k_D0000   =  0x0000026A
+AMD_AP_MTRR_FIX4k_D8000   =  0x0000026B
+AMD_AP_MTRR_FIX4k_E0000   =  0x0000026C
+AMD_AP_MTRR_FIX4k_E8000   =  0x0000026D
+AMD_AP_MTRR_FIX4k_F0000   =  0x0000026E
+AMD_AP_MTRR_FIX4k_F8000   =  0x0000026F
+CPU_LIST_TERMINAL         =  0xFFFFFFFF
+
 AMD_MTRR_DEFTYPE         =      0x02FF
     WB_DRAM_TYPE         =      0x1E             /* MemType - memory type */
     MTRR_DEF_TYPE_EN     =      11               /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 25ae733b4f..ca281725c7 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -42,7 +42,12 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
+#ifdef __x86_64__
+CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
+#else
 CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */
+#endif
 
 APIC_BASE_ADDRESS       =       0x0000001B
   APIC_BSC              =       8               /* Boot Strap Core  */
@@ -61,6 +66,20 @@ AMD_MTRR_FIX4k_E8000     =      0x026D
 AMD_MTRR_FIX4k_F0000     =      0x026E
 AMD_MTRR_FIX4k_F8000     =      0x026F
 
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000  =  0x00000250
+AMD_AP_MTRR_FIX16k_80000  =  0x00000258
+AMD_AP_MTRR_FIX16k_A0000  =  0x00000259
+AMD_AP_MTRR_FIX4k_C0000   =  0x00000268
+AMD_AP_MTRR_FIX4k_C8000   =  0x00000269
+AMD_AP_MTRR_FIX4k_D0000   =  0x0000026A
+AMD_AP_MTRR_FIX4k_D8000   =  0x0000026B
+AMD_AP_MTRR_FIX4k_E0000   =  0x0000026C
+AMD_AP_MTRR_FIX4k_E8000   =  0x0000026D
+AMD_AP_MTRR_FIX4k_F0000   =  0x0000026E
+AMD_AP_MTRR_FIX4k_F8000   =  0x0000026F
+CPU_LIST_TERMINAL         =  0xFFFFFFFF
+
 AMD_MTRR_DEFTYPE         =      0x02FF
     WB_DRAM_TYPE         =      0x1E             /* MemType - memory type */
     MTRR_DEF_TYPE_EN     =      11               /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
@@ -1603,4 +1622,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 80158cd5b3..18376dfaf2 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -42,6 +42,7 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
 #ifdef __x86_64__
 CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
 #else
@@ -1621,4 +1622,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index 80662cfd5d..9d566f2f1b 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -42,7 +42,12 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
+#ifdef __x86_64__
+CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
+#else
 CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */
+#endif
 
 APIC_BASE_ADDRESS       =       0x0000001B
   APIC_BSC              =       8               /* Boot Strap Core  */
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index 1701a213f3..330570e3e9 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -42,7 +42,12 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
+#ifdef __x86_64__
+CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
+#else
 CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */
+#endif
 
 APIC_BASE_ADDRESS       =       0x0000001B
   APIC_BSC              =       8               /* Boot Strap Core  */
@@ -1933,4 +1938,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 87e609087b..592ee6d00e 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -42,7 +42,12 @@ BSP_STACK_SIZE          =       0x10000         /* 64KB for BSP core
 CORE0_STACK_BASE_ADDR   =       0x80000         /* Base address for primary cores stack   */
 CORE0_STACK_SIZE        =       0x4000          /* 16KB for primary cores                 */
 CORE1_STACK_BASE_ADDR   =       0x40000         /* Base address for AP cores              */
+
+#ifdef __x86_64__
+CORE1_STACK_SIZE        =       0x2000          /* 8KB for each AP cores                  */
+#else
 CORE1_STACK_SIZE        =       0x1000          /* 4KB for each AP cores                  */
+#endif
 
 APIC_BASE_ADDRESS       =       0x0000001B
   APIC_BSC              =       8               /* Boot Strap Core  */
@@ -1298,4 +1303,3 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
     xor     %eax, %eax
 
 .endm
-