diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2018-09-11 13:49:45 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-09-13 08:25:59 +0000 |
| commit | a52016cc46cdf0672448d9f25060c3c35e8919c4 (patch) | |
| tree | 9bb156a650d7a3e2bf12e7318e277efce3c1b73d | |
| parent | ef8b95745f4b72439fb5f108acf0a62361f64101 (diff) | |
src/*/intel: introduce warning when building with no IFD
Add a warning as suggested in patch CB:28233 with the
"CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED" option.
Change-Id: I42b6b336bb519f3d18b5a41eb20b380636ff5819
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/common/firmware/Makefile.inc | 11 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/Kconfig | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/Kconfig | 5 |
4 files changed, 26 insertions, 1 deletions
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 73e01cdcc4..0f75537247 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -31,6 +31,12 @@ config INTEL_DESCRIPTOR_MODE_CAPABLE This config simply states that the platform is *capable* of running in descriptor mode (when the descriptor in flash is valid). +config INTEL_DESCRIPTOR_MODE_REQUIRED + def_bool y if INTEL_DESCRIPTOR_MODE_CAPABLE + help + This config states descriptor mode is *required* for the platform to + function properly, or to function at all. + config INTEL_CHIPSET_LOCKDOWN depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS #ChromeOS's payload seems to handle finalization on its on. diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 426863c658..01a80614e3 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -22,6 +22,8 @@ ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) ifeq ($(CONFIG_HAVE_IFD_BIN),y) INTERMEDIATE+=add_intel_firmware +else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) +INTERMEDIATE += warn_intel_firmware endif IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) @@ -85,6 +87,13 @@ ifeq ($(CONFIG_EM100),y) mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif -PHONY+=add_intel_firmware +warn_intel_firmware: + printf "\n\t** WARNING **\n" + printf "coreboot will be built without an Intel Firmware Descriptor.\n" + printf "Never write a complete coreboot.rom without an IFD to your\n" + printf "board's flash chip! You can use flashrom's IFD or layout\n" + printf "parameters to flash only to the BIOS region.\n\n" + +PHONY+=add_intel_firmware warn_intel_firmware endif diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 9e88a2830b..0c5aabfc40 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -36,6 +36,11 @@ config EHCI_BAR hex default 0xfef00000 +## Some enterprise variants may require an IFD +config INTEL_DESCRIPTOR_MODE_REQUIRED + bool + default n + config HPET_MIN_TICKS hex default 0x80 diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index bf2d01fb20..cb5b12fcd0 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -36,6 +36,11 @@ config EHCI_BAR hex default 0xfef00000 +## Some enterprise variants may require an IFD +config INTEL_DESCRIPTOR_MODE_REQUIRED + bool + default n + config HPET_MIN_TICKS hex default 0x80 |