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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2020-01-10 12:48:20 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-14 17:02:30 +0000 |
| commit | a1114f608b99f0e847fc41807443133513ab734a (patch) | |
| tree | 76222a618288d70e76b07872698eaa3c9262c569 | |
| parent | 63ae8dec797098f65c409842d4825730fecd79d2 (diff) | |
autoport: Add Xeon E3-1200 v2 memory controller ID
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Change-Id: Ic5f18669a04397f570d49c1ff056cd90b3eb04a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | util/autoport/sandybridge.go | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 718fbe8f37..acfda6b8dd 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -126,6 +126,7 @@ func init() { RegisterPCI(0x8086, 0x0104, sandybridgemc{}) RegisterPCI(0x8086, 0x0150, sandybridgemc{}) RegisterPCI(0x8086, 0x0154, sandybridgemc{}) + RegisterPCI(0x8086, 0x0158, sandybridgemc{}) for _, id := range []uint16{ 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, |