summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAntonello Dettori <dev@dettori.io>2016-11-08 18:44:46 +0100
committerPatrick Georgi <pgeorgi@google.com>2017-03-23 18:52:21 +0100
commit9709af3521969e8c0583952bc24077f5f0dd9617 (patch)
tree2585e19c7cac27e5fb0b688a33a361b9900942b5
parent6b542faf202757d6525a31a8e29e1e69540c12e5 (diff)
mainboard/samsung/stumpy: transition away from device_t
Replace the use of the old device_t definition inside mainboard/samsung/stumpy. Change-Id: Ie6209b3b40d9aad0723690e7aeb3edfd0bfcc4a8 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17304 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/mainboard/samsung/stumpy/chromeos.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index 96d2b125d7..01d81d73c5 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -84,10 +84,11 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_write_protect_state(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
@@ -95,10 +96,11 @@ int get_write_protect_state(void)
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
@@ -106,10 +108,11 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 2);
#else
+ device_t dev;
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
#endif
return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;