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authorVaibhav Shankar <vaibhav.shankar@intel.com>2018-03-19 19:04:16 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-03-23 08:56:34 +0000
commit8cf149007fb0802125fa7b90025a10d4c365d426 (patch)
treeacc61a1dde9b5542635f49c67c0b858cdca87b1c
parent2da6ec40bbbf9b30afd4372587235d14a455f88f (diff)
mainboard/intel/cannonlake_rvp: Enable S0ix
This patch enables S0ix from the devicetree. Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25293 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb3
-rw-r--r--src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 3e60ed946b..18aa65d890 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -70,6 +70,9 @@ chip soc/intel/cannonlake
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
# Audio
register "i2c[3]" = "{
.speed = I2C_SPEED_STANDARD,
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8502048880..6dd1893948 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -68,6 +68,9 @@ chip soc/intel/cannonlake
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPP_G5"
+ # Enable S0ix
+ register "s0ix_enable" = "1"
+
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device