google/veyron*: add DDR configs for new samsung DDR

Add the new samsung DDR configs for all veyron except veyron_rialto:
* K4E6E304EB-EGCE, ramid = 0010, 4GB
* K4E8E324EB-EGCF, ramid = 1100, 2GB

BRANCH=veyron
BUG=none
TEST=boot fievel board

Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c
Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345748
Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7)
Original-Reviewed-on: https://chromium-review.googlesource.com/404690
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

18 files changed, 948 insertions, 12 deletions

diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c
index aaa0bf34d5..76e4f765d1 100644
--- a/src/mainboard/google/veyron/sdram_configs.c
+++ b/src/mainboard/google/veyron/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c
index aaa0bf34d5..76e4f765d1 100644
--- a/src/mainboard/google/veyron_brain/sdram_configs.c
+++ b/src/mainboard/google/veyron_brain/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c
index 8f53088863..c7f2055d16 100644
--- a/src/mainboard/google/veyron_danger/sdram_configs.c
+++ b/src/mainboard/google/veyron_danger/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_emile/sdram_configs.c b/src/mainboard/google/veyron_emile/sdram_configs.c
index aaa0bf34d5..76e4f765d1 100644
--- a/src/mainboard/google/veyron_emile/sdram_configs.c
+++ b/src/mainboard/google/veyron_emile/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c
index aaa0bf34d5..76e4f765d1 100644
--- a/src/mainboard/google/veyron_mickey/sdram_configs.c
+++ b/src/mainboard/google/veyron_mickey/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c
index aaa0bf34d5..76e4f765d1 100644
--- a/src/mainboard/google/veyron_romy/sdram_configs.c
+++ b/src/mainboard/google/veyron_romy/sdram_configs.c
@@ -23,7 +23,7 @@
 static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc"	/* ram_code = 0000 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc"		/* ram_code = 0001 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 0010 */
+#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc"	/* ram_code = 0010 */
 #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc"	/* ram_code = 0011 */
 #include "sdram_inf/sdram-ddr3-samsung-2GB.inc"		/* ram_code = 0100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 0101 */
@@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = {
 #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc"		/* ram_code = 1001 */
 #include "sdram_inf/sdram-ddr3-nanya-2GB.inc"		/* ram_code = 1010 */
 #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc"	/* ram_code = 1011 */
-#include "sdram_inf/sdram-unused.inc"			/* ram_code = 1100 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc"	/* ram_code = 1100 */
 #include "sdram_inf/sdram-ddr3-hynix-2GB.inc"		/* ram_code = 1101 */
 #include "sdram_inf/sdram-ddr3-samsung-4GB.inc"		/* ram_code = 1110 */
 #include "sdram_inf/sdram-ddr3-hynix-4GB.inc"		/* ram_code = 1111 */
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
new file mode 100644
index 0000000000..a4bfb01ab7
--- /dev/null
+++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E8E324EB-EGCF chips */
+	{
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x1,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 14,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 9,
+	.odt = 0,
+},
diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
new file mode 100644
index 0000000000..6b6df57a49
--- /dev/null
+++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc
@@ -0,0 +1,78 @@
+{
+	/* 2 Samsung K4E6E304EB-EGCE chips */
+	{
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		},
+		{
+			.rank = 0x2,
+			.col = 0xA,
+			.bk = 0x3,
+			.bw = 0x2,
+			.dbw = 0x2,
+			.row_3_4 = 0x0,
+			.cs0_row = 0xF,
+			.cs1_row = 0xF
+		}
+	},
+	{
+		.togcnt1u = 0x215,
+		.tinit = 0xC8,
+		.trsth = 0x0,
+		.togcnt100n = 0x35,
+		.trefi = 0x26,
+		.tmrd = 0x2,
+		.trfc = 0x70,
+		.trp = 0x2000D,
+		.trtw = 0x6,
+		.tal = 0x0,
+		.tcl = 0x8,
+		.tcwl = 0x4,
+		.tras = 0x17,
+		.trc = 0x24,
+		.trcd = 0xD,
+		.trrd = 0x6,
+		.trtp = 0x4,
+		.twr = 0x8,
+		.twtr = 0x4,
+		.texsr = 0x76,
+		.txp = 0x4,
+		.txpdll = 0x0,
+		.tzqcs = 0x30,
+		.tzqcsi = 0x0,
+		.tdqs = 0x1,
+		.tcksre = 0x2,
+		.tcksrx = 0x2,
+		.tcke = 0x4,
+		.tmod = 0x0,
+		.trstl = 0x0,
+		.tzqcl = 0xC0,
+		.tmrr = 0x4,
+		.tckesr = 0x8,
+		.tdpd = 0x1F4
+	},
+	{
+		.dtpr0 = 0x48D7DD93,
+		.dtpr1 = 0x187008D8,
+		.dtpr2 = 0x121076,
+		.mr[0] = 0x0,
+		.mr[1] = 0xC3,
+		.mr[2] = 0x6,
+		.mr[3] = 0x1
+	},
+	.noc_timing = 0x20D266A4,
+	.noc_activate = 0x5B6,
+	.ddrconfig = 3,
+	.ddr_freq = 533*MHz,
+	.dramtype = LPDDR3,
+	.num_channels = 2,
+	.stride = 13,
+	.odt = 0,
+},