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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-29 18:11:16 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-09-02 07:16:05 +0000
commit694cbc0ddcbe04dbbbb4f97ae4d34861a6ce7054 (patch)
treee5255a1e9cb99fcc8f193fb7ac86074816e8254a
parent1d418281e098159339e292c1a4f0dde4bf35122c (diff)
{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/northbridge/intel/haswell/memmap.c2
-rw-r--r--src/soc/intel/broadwell/memmap.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index a86efeb788..807ee2a358 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -18,7 +18,7 @@ static uintptr_t smm_region_start(void)
* 1 MiB alignment.
*/
uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG);
- return tom & ~((1 << 20) - 1);
+ return ALIGN_DOWN(tom, 1 * MiB);
}
void *cbmem_top_chipset(void)
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index bada5fd1c1..4673cceca0 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -18,7 +18,7 @@ static uintptr_t dpr_region_start(void)
* must be calculated from the size in MiB in bits 11:4.
*/
uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
- uintptr_t tom = dpr & ~((1 << 20) - 1);
+ uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
/* Subtract DMA Protected Range size if enabled */
if (dpr & DPR_EPM)