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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-02-05 08:12:20 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-06-05 10:15:39 +0200
commit57978a363e6381a378d2319e77ff15a1481ac7ae (patch)
treef866aa24dacf5719ba5e9c977deb4ac709a26d35
parenta9f4327d0f40f53fba5ca690f52b98e12236e236 (diff)
AMD K8 fam10: Eliminate local variable min_bus
Some cases of max==0xff wrapping around the 8-bit link->secondary register remain to be solved. Change-Id: I01e2ab6b2f23a03dbac49207ab584eccd1ca9b1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8364 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c19
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c16
2 files changed, 14 insertions, 21 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index caf5410618..efd8a7057e 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -199,7 +199,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
unsigned int next_unitid;
u32 ht_c_index;
u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
- u32 min_bus;
u32 max_devfn;
/* Check for connected link. */
@@ -220,25 +219,21 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
*/
if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
- min_bus = ++max;
+ max++;
} else if (is_sblink) {
- // first chain will on bus 0
- min_bus = max; /* actually max is 0 here */
+
} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
- min_bus = ++max;
+ max++;
} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
- // second chain will be on 0x40, third 0x80, forth 0xc0
- // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0
- // >4 will use more segments,
// We can have 16 segmment and every segment have 256 bus,
// For that case need the kernel support mmio pci config.
/* One node can have 8 link and segn is the same. */
- min_bus = (((max & 0xff) >> 3) + 1) << 3;
- max = min_bus;
+ max++;
+ max = ALIGN_UP(max, 8);
}
- link->secondary = min_bus;
+ link->secondary = max;
link->subordinate = link->secondary;
ht_route_link(link, HT_ROUTE_SCAN);
@@ -255,7 +250,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
}
//if ext conf is enabled, only need use 0x1f
- if (min_bus == 0)
+ if (link->secondary == 0)
max_devfn = (0x17<<3) | 7;
else
max_devfn = (0x1f<<3) | 7;
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index b27404e6e7..7826749122 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -141,7 +141,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
u32 config_busses;
u32 free_reg, config_reg;
u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
- u32 min_bus;
u32 max_devfn;
link->cap = 0x80 + (link->link_num * 0x20);
@@ -180,19 +179,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
* so we set the subordinate bus number to 0xff for the moment.
*/
if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
- min_bus = ++max;
+ max++;
} else if (is_sblink) {
- // first chain will on bus 0
- min_bus = max; /* actually max is 0 here */
+
} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
- min_bus = ++max;
+ max++;
} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
- min_bus = (max & ~0x3f) + 0x40;
- max = min_bus;
+ max++;
+ max = ALIGN_UP(max, 0x40);
}
- link->secondary = min_bus;
+ link->secondary = max;
link->subordinate = link->secondary;
ht_route_link(link, HT_ROUTE_SCAN);
@@ -214,7 +212,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
ht_unitid_base[i] = 0x20;
}
- if (min_bus == 0)
+ if (link->secondary == 0)
max_devfn = (0x17<<3) | 7;
else
max_devfn = (0x1f<<3) | 7;