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authorFurquan Shaikh <furquan@chromium.org>2017-03-31 13:49:31 -0700
committerFurquan Shaikh <furquan@google.com>2017-04-05 20:26:03 +0200
commit3255839be15bcccde652891354e91965733f8a86 (patch)
treef5226b0806f8196bd944c02dcd3849ddcf9ffacd
parent580e0c584f1ba0f5196c2a3880b55592909d9df4 (diff)
soc/intel/skylake: Add tsc_freq.c to verstage
This is required to provide tsc freq required by timer library. BUG=b:35583330 TEST=Verified that delay(5) in verstage adds a delay of 5 seconds. Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19094 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/intel/skylake/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index f7b4971869..f9c267e435 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -33,6 +33,7 @@ verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c
verstage-y += bootblock/i2c.c
verstage-y += spi.c
+verstage-y += tsc_freq.c
romstage-y += flash_controller.c
romstage-y += gpio.c