soc/intel/tigerlake: Update chip files

Update chip files to include :
  - Update chip.c based on TGL FSP
  - Update chip.h based on TGL FSP
  - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
  - Update pmc_utils.c and JSL devicetree for build failure

Reference
PCH EDS#576591 vol1 rev1.2

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 73 insertions, 94 deletions

diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index b4ed69744b..854df4656b 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -8,9 +8,9 @@ chip soc/intel/tigerlake
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE
 	# offset bits also need to be changed.
-	register "gpe0_dw0" = "GPP_B"
-	register "gpe0_dw1" = "GPP_D"
-	register "gpe0_dw2" = "GPP_E"
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index f1ae8a82c9..9340f6980c 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -115,6 +115,11 @@ config MAX_ROOT_PORTS
 	default 16 if SOC_INTEL_JASPERLAKE
 	default 12 if SOC_INTEL_TIGERLAKE
 
+config MAX_PCIE_CLOCKS
+	int
+	default 7 if SOC_INTEL_TIGERLAKE
+	default 16 if SOC_INTEL_JASPERLAKE
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index d05fbdfdde..2637cf8482 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -34,29 +34,51 @@ const char *soc_acpi_name(const struct device *dev)
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
 		return "PCI0";
 
+	if (dev->path.type == DEVICE_PATH_USB) {
+		switch (dev->path.usb.port_type) {
+		case 0:
+			/* Root Hub */
+			return "RHUB";
+		case 2:
+			/* USB2 ports */
+			switch (dev->path.usb.port_id) {
+			case 0: return "HS01";
+			case 1: return "HS02";
+			case 2: return "HS03";
+			case 3: return "HS04";
+			case 4: return "HS05";
+			case 5: return "HS06";
+			case 6: return "HS07";
+			case 7: return "HS08";
+			case 8: return "HS09";
+			case 9: return "HS10";
+			}
+			break;
+		case 3:
+			/* USB3 ports */
+			switch (dev->path.usb.port_id) {
+			case 0: return "SS01";
+			case 1: return "SS02";
+			case 2: return "SS03";
+			case 3: return "SS04";
+			}
+			break;
+		}
+		return NULL;
+	}
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return NULL;
 
 	switch (dev->path.pci.devfn) {
 	case SA_DEVFN_ROOT:	return "MCHC";
-	case SA_DEVFN_IGD:	return "GFX0";
-	case PCH_DEVFN_ISH:	return "ISHB";
 	case PCH_DEVFN_XHCI:	return "XHCI";
-	case PCH_DEVFN_USBOTG:	return "XDCI";
-	case PCH_DEVFN_THERMAL:	return "THRM";
 	case PCH_DEVFN_I2C0:	return "I2C0";
 	case PCH_DEVFN_I2C1:	return "I2C1";
 	case PCH_DEVFN_I2C2:	return "I2C2";
 	case PCH_DEVFN_I2C3:	return "I2C3";
-	case PCH_DEVFN_CSE:	return "CSE1";
-	case PCH_DEVFN_CSE_2:	return "CSE2";
-	case PCH_DEVFN_CSE_IDER:	return "CSED";
-	case PCH_DEVFN_CSE_KT:	return "CSKT";
-	case PCH_DEVFN_CSE_3:	return "CSE3";
-	case PCH_DEVFN_SATA:	return "SATA";
-	case PCH_DEVFN_UART2:	return "UAR2";
 	case PCH_DEVFN_I2C4:	return "I2C4";
 	case PCH_DEVFN_I2C5:	return "I2C5";
+	case PCH_DEVFN_SATA:	return "SATA";
 	case PCH_DEVFN_PCIE1:	return "RP01";
 	case PCH_DEVFN_PCIE2:	return "RP02";
 	case PCH_DEVFN_PCIE3:	return "RP03";
@@ -69,34 +91,17 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_PCIE10:	return "RP10";
 	case PCH_DEVFN_PCIE11:	return "RP11";
 	case PCH_DEVFN_PCIE12:	return "RP12";
-	case PCH_DEVFN_PCIE13:	return "RP13";
-	case PCH_DEVFN_PCIE14:	return "RP14";
-	case PCH_DEVFN_PCIE15:	return "RP15";
-	case PCH_DEVFN_PCIE16:	return "RP16";
-	case PCH_DEVFN_PCIE17:	return "RP17";
-	case PCH_DEVFN_PCIE18:	return "RP18";
-	case PCH_DEVFN_PCIE19:	return "RP19";
-	case PCH_DEVFN_PCIE20:	return "RP20";
-	case PCH_DEVFN_PCIE21:	return "RP21";
-	case PCH_DEVFN_PCIE22:	return "RP22";
-	case PCH_DEVFN_PCIE23:	return "RP23";
-	case PCH_DEVFN_PCIE24:	return "RP24";
 	case PCH_DEVFN_UART0:	return "UAR0";
 	case PCH_DEVFN_UART1:	return "UAR1";
+	case PCH_DEVFN_UART2:	return "UAR2";
 	case PCH_DEVFN_GSPI0:	return "SPI0";
 	case PCH_DEVFN_GSPI1:	return "SPI1";
 	case PCH_DEVFN_GSPI2:	return "SPI2";
-	case PCH_DEVFN_EMMC:	return "EMMC";
-	case PCH_DEVFN_SDCARD:	return "SDXC";
 	/* Keeping ACPI device name coherent with ec.asl */
 	case PCH_DEVFN_ESPI:	return "LPCB";
-	case PCH_DEVFN_P2SB:	return "P2SB";
-	case PCH_DEVFN_PMC:	return "PMC_";
 	case PCH_DEVFN_HDA:	return "HDAS";
 	case PCH_DEVFN_SMBUS:	return "SBUS";
-	case PCH_DEVFN_SPI:	return "FSPI";
-	case PCH_DEVFN_GBE:	return "IGBE";
-	case PCH_DEVFN_TRACEHUB:return "THUB";
+	case PCH_DEVFN_GBE:	return "GLAN";
 	}
 
 	return NULL;
@@ -146,9 +151,9 @@ static struct device_operations pci_domain_ops = {
 	.read_resources   = &pci_domain_read_resources,
 	.set_resources    = &pci_domain_set_resources,
 	.scan_bus         = &pci_domain_scan_bus,
-	#if CONFIG(HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
 	.acpi_name        = &soc_acpi_name,
-	#endif
+#endif
 };
 
 static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 5e0fcd11c5..4907f4921d 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -36,10 +36,10 @@ struct soc_intel_tigerlake_config {
 	struct soc_intel_common_config common_soc_config;
 
 	/* Gpio group routed to each dword of the GPE0 block. Values are
-	 * of the form GPP_[A:G] or GPD. */
-	uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
-	uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
-	uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
+	 * of the form PMC_GPP_[A:U] or GPD. */
+	uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
+	uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
+	uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
 
 	/* Generic IO decode ranges */
 	uint32_t gen1_dec;
@@ -67,43 +67,25 @@ struct soc_intel_tigerlake_config {
 	/* TCC activation offset */
 	uint32_t tcc_offset;
 
-	uint64_t PlatformMemorySize;
-	uint8_t SmramMask;
-	uint8_t MrcFastBoot;
-	uint32_t TsegSize;
-	uint16_t MmioSize;
-
-	/* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz.
-	 * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
-	uint16_t DdrFreqLimit;
-
-	/* SAGV Low Frequency Selections in Mhz.
-	 * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
-	uint16_t FreqSaGvLow;
-
-	/* SAGV Mid Frequency Selections in Mhz.
-	 * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */
-	uint16_t FreqSaGvMid;
-
 	/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
 	 * When enabled memory will be training at two different frequencies.
-	 * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */
+	 * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
+	 * 4:FixedPoint3, 5:Enabled */
 	enum {
 		SaGv_Disabled,
-		SaGv_FixedLow,
-		SaGv_FixedMid,
-		SaGv_FixedHigh,
+		SaGv_FixedPoint0,
+		SaGv_FixedPoint1,
+		SaGv_FixedPoint2,
+		SaGv_FixedPoint3,
 		SaGv_Enabled,
 	} SaGv;
 
-
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
 
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];
 	struct usb3_port_config usb3_ports[10];
-	uint8_t SsicPortEnable;
 	/* Wake Enable Bitmap for USB2 ports */
 	uint16_t usb2_wake_enable_bitmap;
 	/* Wake Enable Bitmap for USB3 ports */
@@ -137,24 +119,16 @@ struct soc_intel_tigerlake_config {
 	/* PCIe output clocks type to Pcie devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
 	/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 	 * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
 
 	/* SMBus */
 	uint8_t SmbusEnable;
 
 	/* eMMC and SD */
 	uint8_t ScsEmmcHs400Enabled;
-	/* Need to update DLL setting to get Emmc running at HS400 speed */
-	uint8_t EmmcUseCustomDlls;
-	uint32_t EmmcTxCmdDelayRegValue;
-	uint32_t EmmcTxDataDelay1RegValue;
-	uint32_t EmmcTxDataDelay2RegValue;
-	uint32_t EmmcRxCmdDataDelay1RegValue;
-	uint32_t EmmcRxCmdDataDelay2RegValue;
-	uint32_t EmmcRxStrobeDelayRegValue;
 
 	/* Enable if SD Card Power Enable Signal is Active High */
 	uint8_t SdCardPowerEnableActiveHigh;
@@ -173,14 +147,6 @@ struct soc_intel_tigerlake_config {
 	uint32_t GraphicsConfigPtr;
 	uint8_t Device4Enable;
 
-	/* GPIO IRQ Select. The valid value is 14 or 15 */
-	uint8_t GpioIrqRoute;
-	/* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
-	uint8_t SciIrqSelect;
-	/* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */
-	uint8_t TcoIrqSelect;
-	uint8_t TcoIrqEnable;
-
 	/* HeciEnabled decides the state of Heci1 at end of boot
 	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
 	uint8_t HeciEnabled;
@@ -188,21 +154,23 @@ struct soc_intel_tigerlake_config {
 	uint32_t tdp_pl2_override;
 	/* Intel Speed Shift Technology */
 	uint8_t speed_shift_enable;
-	/* Enable VR specific mailbox command
-	 * 00b - no VR specific cmd sent
-	 * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent
-	 * 10b - VR specific cmd sent for PS4 exit issue
-	 * 11b - Reserved */
-	uint8_t SendVrMbxCmd;
 
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
 
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;
-
+	/*
+	 * PRMRR size setting with below options
+	 * Disable: 0x0
+	 * 32MB: 0x2000000
+	 * 64MB: 0x4000000
+	 * 128 MB: 0x8000000
+	 * 256 MB: 0x10000000
+	 * 512 MB: 0x20000000
+	 */
+	uint32_t PrmrrSize;
 	uint8_t PmTimerDisabled;
-
 	/* Desired platform debug type. */
 	enum {
 		DebugConsent_Disabled,
@@ -211,6 +179,8 @@ struct soc_intel_tigerlake_config {
 		DebugConsent_USB3_DBC,
 		DebugConsent_XDP, /* XDP/Mipi60 */
 		DebugConsent_USB2_DBC,
+		DebugConsent_2WIRE_DCI,
+		DebugConsent_Manual,
 	} DebugConsent;
 	/*
 	 * SerialIO device mode selection:
@@ -244,9 +214,8 @@ struct soc_intel_tigerlake_config {
 
 	/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 	enum {
-		PLATFORM_POR,
-		FORCE_ENABLE,
 		FORCE_DISABLE,
+		FORCE_ENABLE,
 	} CnviBtAudioOffload;
 
 	/*
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c
index 39734bb4e9..84a93aebbc 100644
--- a/src/soc/intel/tigerlake/pmutil.c
+++ b/src/soc/intel/tigerlake/pmutil.c
@@ -189,9 +189,9 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	config = config_of_soc();
 
 	/* Assign to out variable */
-	*dw0 = config->gpe0_dw0;
-	*dw1 = config->gpe0_dw1;
-	*dw2 = config->gpe0_dw2;
+	*dw0 = config->pmc_gpe0_dw0;
+	*dw1 = config->pmc_gpe0_dw1;
+	*dw2 = config->pmc_gpe0_dw2;
 }
 
 static int rtc_failed(uint32_t gen_pmcon_b)