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authorEdward O'Callaghan <quasisec@google.com>2019-12-20 11:47:29 +1100
committerEdward O'Callaghan <quasisec@chromium.org>2019-12-23 22:09:48 +0000
commit295fdbef392e1ab6c8c7e4f0d7a9a01d95bb5bd5 (patch)
treedc8f8f3100fbd0d237530d6dc158ee2795221082
parente8b7ff1ab51be3fd8a98a3fc1dfdf15aa800cab5 (diff)
mainboard/google/puff: Configure HDA registers
Enable PCH HDA and configure dmic+ssp registers. BRANCH=none BUG=b:146519004 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: If9495261201ca256cdb35352338c0b3a82a50196 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
-rw-r--r--src/mainboard/google/hatch/variants/puff/overridetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index b99c1f240a..342994d90a 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -68,6 +68,10 @@ chip soc/intel/cannonlake
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
+ # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
+ register "PchHdaAudioLinkSsp1" = "0"
+ register "PchHdaAudioLinkDmic0" = "0"
+
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |