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authorzbao <fishbaozi@gmail.com>2015-11-05 20:25:59 +0800
committerZheng Bao <zheng.bao@amd.com>2015-11-06 07:53:00 +0100
commit1897c2c3508f3d5e2d020c6e56f16611c8cfad4a (patch)
treec3c938dec8e37d0375a791bb96f38fd7aa963fad
parentaeb2103ab5184d46dc315f616acbf521f3aa1ab4 (diff)
AMD Bettong: Enable S4 feature for Windows 7
PMIOxEE is for setting USB3 power rail. Set it to S0, otherwise going into hibernation can not be wake up. Change-Id: I692497bad24d745738d670897e725a568c1db114 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11373 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/arch/x86/acpi.c6
-rw-r--r--src/arch/x86/include/arch/acpi.h2
-rw-r--r--src/mainboard/amd/bettong/romstage.c6
3 files changed, 14 insertions, 0 deletions
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 55995c9542..c540b5ce4c 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -1005,6 +1005,12 @@ int acpi_is_wakeup_s3(void)
return (acpi_slp_type == 3);
}
+int acpi_is_wakeup_s4(void)
+{
+ acpi_handoff_wakeup();
+ return (acpi_slp_type == 4);
+}
+
void acpi_fail_wakeup(void)
{
if (acpi_slp_type == 3 || acpi_slp_type == 2)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 66e11006dc..87810b6b44 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -596,12 +596,14 @@ static inline int acpi_is_wakeup_s3(void)
#else
int acpi_is_wakeup(void);
int acpi_is_wakeup_s3(void);
+int acpi_is_wakeup_s4(void);
#endif
#else
#define acpi_slp_type 0
static inline int acpi_is_wakeup(void) { return 0; }
static inline int acpi_is_wakeup_s3(void) { return 0; }
+static inline int acpi_is_wakeup_s4(void) { return 0; }
#endif
#endif /* __ASM_ACPI_H */
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 9f94d7b6c5..6399804ac2 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <arch/acpi.h>
+#include <arch/io.h>
#include <arch/stages.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
@@ -78,6 +79,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
prepare_for_resume();
}
+ if (s3resume || acpi_is_wakeup_s4()) {
+ outb(0xEE, PM_INDEX);
+ outb(0x8, PM_DATA);
+ }
+
post_code(0x50);
copy_and_run();