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authorAaron Durbin <adurbin@chromium.org>2013-07-03 16:21:28 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-07 03:51:52 +0100
commit16cbf8983c2481a31357f25c44a09b670edcf870 (patch)
treedf7e3ee1161e3ceab4647a05ca34b9facd1a4849
parent01ab2d14be086bd6fda82eaad000a34e6abb9047 (diff)
haswell: VR controller configuration
Configure the VR controller. This enables the PSIx levels as well as C-state ramping. PSIx thresholds are: - PSI3: 1A. - PSI2: 5A. - PSI1: 15A. Before: 0x601 0x0000000000000100 0x603 0x0036000000262626 0x636 0x000000000000006f After: 0x601 0x4010140f00000100 0x603 0x0036000000262626 0x636 0x000000000000006f Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60931 Reviewed-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: http://review.coreboot.org/4338 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/cpu/intel/haswell/haswell.h2
-rw-r--r--src/cpu/intel/haswell/haswell_init.c53
2 files changed, 55 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 387521722a..e8c224944a 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -83,9 +83,11 @@
#define PKG_POWER_LIMIT_TIME_MASK 0x7f
#define MSR_VR_CURRENT_CONFIG 0x601
+#define MSR_VR_MISC_CONFIG 0x603
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_SKU 0x614
#define MSR_DDR_RAPL_LIMIT 0x618
+#define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index fb78df419a..adc99cfd48 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -293,6 +293,57 @@ static u32 pcode_mailbox_read(u32 command)
return MCHBAR32(BIOS_MAILBOX_DATA);
}
+static void initialize_vr_config(void)
+{
+ msr_t msr;
+
+ printk(BIOS_DEBUG, "Initializing VR config.\n");
+
+ /* Configure VR_CURRENT_CONFIG. */
+ msr = rdmsr(MSR_VR_CURRENT_CONFIG);
+ /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
+ * on ULT systems. */
+ msr.hi &= 0xc0000000;
+ msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */
+ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */
+ msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
+
+ if (is_ult())
+ msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
+ /* Leave the max instantaneous current limit (12:0) to default. */
+ wrmsr(MSR_VR_CURRENT_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG MSR. */
+ msr = rdmsr(MSR_VR_MISC_CONFIG);
+ /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */
+ msr.hi &= ~(0x3ff << (40 - 32));
+ msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
+ /* Set IOUT_OFFSET to 0. */
+ msr.hi &= ~0xff;
+ /* Set exit ramp rate to fast. */
+ msr.hi |= (1 << (50 - 32));
+ /* Set entry ramp rate to slow. */
+ msr.hi &= ~(1 << (51 - 32));
+ /* Enable decay mode on C-state entry. */
+ msr.hi |= (1 << (52 - 32));
+ /* Set the slow ramp rate to be fast ramp rate / 4 */
+ msr.hi &= ~(0x3 << (53 - 32));
+ msr.hi |= (0x01 << (53 - 32));
+ /* Set MIN_VID (31:24) to allow CPU to have full control. */
+ msr.lo &= ~0xff000000;
+ wrmsr(MSR_VR_MISC_CONFIG, msr);
+
+ /* Configure VR_MISC_CONFIG2 MSR. */
+ if (is_ult()) {
+ msr = rdmsr(MSR_VR_MISC_CONFIG2);
+ msr.lo &= ~0xffff;
+ /* Allow CPU to control minimum voltage completely (15:8) and
+ * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */
+ msr.lo |= 0x006f;
+ wrmsr(MSR_VR_MISC_CONFIG2, msr);
+ }
+}
+
static void configure_pch_power_sharing(void)
{
u32 pch_power, pch_power_ext, pmsync, pmsync2;
@@ -645,6 +696,8 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);
x86_mtrr_check();
+ initialize_vr_config();
+
if (is_ult()) {
calibrate_24mhz_bclk();
configure_pch_power_sharing();