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authorJimmy Zhang <jimmzhang@nvidia.com>2015-06-03 17:34:41 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-06-17 11:55:06 +0200
commit121b4c09c4d0bd91564c4bcf057224b1d7d4a012 (patch)
tree6c0cc2d53dc612aad24ec0e3f6377495dff29f1f
parent66e93355d1b91ace4a1acdf883606e7af96069d0 (diff)
arm64: Move enabling floating point ahead of dev init
This CL is in preparing for tegra mtc that is invoked by dev init. mtc currently requires floating point instructions support. BUG=chrome-os-partner:40999 BRANCH=none TEST=Build and boot smaug Change-Id: I470dfcd86026812d617f9ff4f4fcdce601195857 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5e3f7336fc7cedf96dab4eff204616519856f831 Original-Change-Id: I14c0003ce76ddf4b4ebb0cf171ea3c62cab55ef9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/275112 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/arch/arm64/cpu_ramstage.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 676590fe17..7b4b26a93d 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -118,12 +118,6 @@ static void init_this_cpu(void *arg)
/* Initialize the GIC. */
gic_init();
- if (dev->ops != NULL && dev->ops->init != NULL) {
- dev->initialized = 1;
- printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
- dev->ops->init(dev);
- }
-
/*
* Disable coprocessor traps to EL3:
* TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR
@@ -145,6 +139,12 @@ static void init_this_cpu(void *arg)
/* Arch Timer init: setup cntfrq per CPU */
arm64_arch_timer_init();
+
+ if (dev->ops != NULL && dev->ops->init != NULL) {
+ dev->initialized = 1;
+ printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
+ dev->ops->init(dev);
+ }
}
/* Fill in cpu_info structures according to device tree. */