diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-10-03 16:05:20 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-07 19:14:13 +0200 |
| commit | 0910f4e76f05798e1a5d96cb4e7f202b290fb62e (patch) | |
| tree | 76f94191d6733cb156c43d37e49a332cd0fe8fc6 | |
| parent | 7692807f4f27a045c0e3638319528c7ae0873d57 (diff) | |
soc/intel/apollolake: Disable HECI2 device reset on S3 resume
Converged Security Engine (CSE) has a secure variable storage feature.
However, this storage is expected to be reset during S3 resume flow.
Since coreboot does not use secure storage feature, disable HECI2 reset
request. This saves appr. 130ms of resume time.
BUG=chrome-os-partner:56941
BRANCH=none
TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note
FspMemoryInit time is not significantly different from normal boot
time case.
Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2384ceb1cf..1f6a38fecc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -184,6 +184,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd) */ mupd->FspmConfig.SkipCseRbp = IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); + + /* + * Converged Security Engine (CSE) has secure storage functionality. + * HECI2 device can be used to access that functionality. However, part + * of S3 resume flow involves resetting HECI2 which takes 136ms. Since + * coreboot does not use secure storage functionality, instruct FSP to + * skip HECI2 reset. + */ + mupd->FspmConfig.EnableS3Heci2 = 0; } __attribute__ ((weak)) |