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authorShelley Chen <shchen@google.com>2019-03-11 22:02:25 -0700
committerShelley Chen <shchen@google.com>2019-03-18 21:07:54 +0000
commitd0e218384f2c9127f701a41b0b8add08528c1450 (patch)
tree922da04a5f05276bfb9556704938a3c824ba99f9
parent717050d1d27a5c88bf1921da94476d0bfc592d97 (diff)
mb/google/hatch: Set hatch to use SOC_INTEL_COMETLAKE
Move these configs to Kconfig.name as well. BUG=b:127310803 BRANCH=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r--src/mainboard/google/hatch/Kconfig1
-rw-r--r--src/mainboard/google/hatch/Kconfig.name2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 3853c300c4..629b125d93 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -18,7 +18,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
- select SOC_INTEL_WHISKEYLAKE
select SYSTEM_TYPE_LAPTOP
if BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index fa743cdba0..e98bcae73c 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -3,7 +3,9 @@ comment "Hatch"
config BOARD_GOOGLE_HATCH
bool "-> Hatch"
select BOARD_GOOGLE_BASEBOARD_HATCH
+ select SOC_INTEL_COMETLAKE
config BOARD_GOOGLE_HATCH_WHL
bool "-> Hatch_whl"
select BOARD_GOOGLE_BASEBOARD_HATCH
+ select SOC_INTEL_WHISKEYLAKE