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authorJohn Su <john_su@compal.corp-partner.google.com>2018-11-01 14:41:30 +0800
committerFurquan Shaikh <furquan@google.com>2018-11-12 07:02:28 +0000
commitcd40ddfad8c0a9f8dc5bf374b44729b9f6a91854 (patch)
tree6fc97115fa09bb81efbb4ed9a4ffbf9e7be86c36
parent0d6349ee0d95a41aaa06ae89a87cb22e51075b01 (diff)
mb/google/octopus/variants/fleex: Set up tcc offset for fleex
Change tcc offset from 0 to 10 for fleex. Refer to b:117789732#1 BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I481526ab10a16a33fe0cf9528b52b8524e012451 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
-rw-r--r--src/mainboard/google/octopus/variants/fleex/overridetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index b557b62de9..938366202b 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -13,6 +13,8 @@ chip soc/intel/apollolake
#| I2C7 | Touchscreen |
#+-------------------+---------------------------+
+ register "tcc_offset" = "10"
+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,