diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 10:19:05 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:34:57 +0000 |
| commit | cce557b7934c2560ac2ae33e06b6039acd4e6fb9 (patch) | |
| tree | 1ea741a6e1baf9f31ac9424fb0398e27fdc1237e | |
| parent | 4de29d48edb2c760332def9004989d6cdf002f02 (diff) | |
x86: link ramstage like the other architectures
All the other architectures are using the memlayout
for linking ramstage. The last piece to align x86 is
to use arch/header.ld and the macros within memlayout.h
to automaticaly generate the necessary linker script.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11508
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/arch/x86/include/arch/header.ld | 25 | ||||
| -rw-r--r-- | src/arch/x86/ramstage.ld | 24 |
2 files changed, 28 insertions, 21 deletions
diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld new file mode 100644 index 0000000000..dd6cb271fa --- /dev/null +++ b/src/arch/x86/include/arch/header.ld @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index c9b2f17730..0d329dba0b 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -1,25 +1,7 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -ENTRY(_start) - -PHDRS -{ - to_load PT_LOAD; -} +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = CONFIG_RAMBASE; - - INCLUDE "lib/program.ramstage.ld" - - _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) } |