diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-28 19:55:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:43:48 +0000 |
| commit | cb4672885e636206101a3266fd6ae001447d4f5d (patch) | |
| tree | d59bb8267df1605c6e698903f9029aac01c143c1 | |
| parent | 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 (diff) | |
sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/i82371eb/isa.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index efbfb22470..ae35d90b2c 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -27,9 +27,7 @@ static void isa_init(struct device *dev) /* * Enable special cycles, needed for soft poweroff. */ - reg32 = pci_read_config16(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SPECIAL; - pci_write_config16(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL); /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) |