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authorDaisuke Nojiri <dnojiri@chromium.org>2017-10-03 11:55:09 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-04 23:13:44 +0000
commitb0b4fd45e534e03bfc0023a31111215eae391a92 (patch)
treef8b68f959fc278567d3185afe08e9e2a7601fc48
parent47dffa59f35a46ada039dd86a20497caa8f518e8 (diff)
google/fizz: Configure GPP_C23 early
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has to be configured in early_gpio_table. BUG=b:67030973 BRANCH=none TEST=Verify by wpsw_boot and wpsw_cur match. Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/fizz/gpio.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index 13081ec673..ae952862e8 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -270,6 +270,8 @@ static const struct pad_config early_gpio_table[] = {
/* Ensure UART pins are in native mode for H1. */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
+/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, NONE,
+ DEEP), /* SCREW_SPI_WP_STATUS */
};
#endif