diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-08 17:37:48 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-06 18:39:16 +0200 |
| commit | 997d25219b67704ba497a3d67f392a8a743a1782 (patch) | |
| tree | dda9a0e737b764c49d92ebbedd4011e8ed77daac | |
| parent | ea7d4e0901e8ebfb2fe520ba3814c41138aaeb26 (diff) | |
baytrail: fix fadt structure for gpe0 block
The gpe0 block's size was being misreported. Correct
the gpe0 size and use make the FADT fields be more
robust instead instead of hand calculating fields that
are the based on the same size.
This change correctly enables GPE events in the kernel.
Confirmed this by using iotools read the gpe_cnt register.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Confirmed EC's GPE event is enabled (but
still not working).
Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176271
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4956
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/soc/intel/baytrail/acpi.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index 1f358f4579..0bfac46bf3 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -169,7 +169,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->pm1_cnt_len = 2; fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; + fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; fadt->cst_cnt = 0; @@ -198,7 +198,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->reset_value = 6; fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; @@ -212,7 +212,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1b_evt_blk.addrh = 0x0; fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; @@ -226,21 +226,21 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_pm1b_cnt_blk.addrh = 0x0; fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; fadt->x_pm2_cnt_blk.addrh = 0x0; fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; |