diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-24 18:23:23 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-25 03:02:49 +0000 |
| commit | 8d4176109d404dbbaf4689281ccec635c1070e99 (patch) | |
| tree | 2643b92882a2a9d4a37777f9f134ec647521e3b0 | |
| parent | 63ee16075e7e4dee90c0cb9b05caeb91f77bf1e5 (diff) | |
soc/intel/{jsl,tgl}: Refactor gpio_op.asl
Also align GPMO ASL function with TGL.
Change-Id: Ia40af2cba9867838a1f99141481a5e78cffa0111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/soc/intel/jasperlake/acpi/gpio_op.asl | 17 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/gpio_op.asl | 12 |
2 files changed, 14 insertions, 15 deletions
diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl index 683686f3ca..9b9dc4477c 100644 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -43,7 +43,7 @@ Method (STXS, 1, Serialized) { VAL0, 32 } - VAL0 = PAD_CFG0_TX_STATE | VAL0 + VAL0 |= PAD_CFG0_TX_STATE } /* @@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized) { VAL0, 32 } - VAL0 = ~PAD_CFG0_TX_STATE & VAL0 + VAL0 &= ~PAD_CFG0_TX_STATE } /* @@ -76,9 +76,8 @@ Method (GPMO, 2, Serialized) { VAL0, 32 } - Local0 = VAL0 - Local0 = ~PAD_CFG0_MODE_MASK & Local0 - Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + Local0 = ~PAD_CFG0_MODE_MASK & VAL0 + Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK VAL0 = Local0 | Arg1 } @@ -98,9 +97,9 @@ Method (GTXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_TX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_TX_DISABLE | VAL0 + VAL0 &= PAD_CFG0_TX_DISABLE } } @@ -120,8 +119,8 @@ Method (GRXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_RX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_RX_DISABLE | VAL0 + VAL0 |= PAD_CFG0_RX_DISABLE } } diff --git a/src/soc/intel/tigerlake/acpi/gpio_op.asl b/src/soc/intel/tigerlake/acpi/gpio_op.asl index f7332aa137..9b9dc4477c 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_op.asl +++ b/src/soc/intel/tigerlake/acpi/gpio_op.asl @@ -43,7 +43,7 @@ Method (STXS, 1, Serialized) { VAL0, 32 } - VAL0 = PAD_CFG0_TX_STATE | VAL0 + VAL0 |= PAD_CFG0_TX_STATE } /* @@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized) { VAL0, 32 } - VAL0 = ~PAD_CFG0_TX_STATE & VAL0 + VAL0 &= ~PAD_CFG0_TX_STATE } /* @@ -97,9 +97,9 @@ Method (GTXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_TX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_TX_DISABLE | VAL0 + VAL0 &= PAD_CFG0_TX_DISABLE } } @@ -119,8 +119,8 @@ Method (GRXE, 2, Serialized) } If (Arg1 == 1) { - VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + VAL0 &= ~PAD_CFG0_RX_DISABLE } ElseIf (Arg1 == 0){ - VAL0 = PAD_CFG0_RX_DISABLE | VAL0 + VAL0 |= PAD_CFG0_RX_DISABLE } } |