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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-07-24 14:29:06 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-12-31 17:32:24 +0100
commit7100cf2b404887e4f196286e72232153ba3f0524 (patch)
tree0c0f6f4d436240c097a183b087f2e7fe025bc9b5
parent1136447a37749135dfe172da56f9c06f3d50c664 (diff)
imgtec/pistachio: Add SOC_REGISTERS memory region
When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
-rw-r--r--src/arch/mips/include/arch/memlayout.h2
-rw-r--r--src/include/symbols.h4
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld2
3 files changed, 8 insertions, 0 deletions
diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h
index 1fc7c74c93..fe05bd8ae5 100644
--- a/src/arch/mips/include/arch/memlayout.h
+++ b/src/arch/mips/include/arch/memlayout.h
@@ -26,4 +26,6 @@
#define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K)
+#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4)
+
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/include/symbols.h b/src/include/symbols.h
index aa055ec852..662f44e34c 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -72,6 +72,10 @@ extern u8 _dma_coherent[];
extern u8 _edma_coherent[];
#define _dma_coherent_size (_edma_coherent - _dma_coherent)
+extern u8 _soc_registers[];
+extern u8 _esoc_registers[];
+#define _soc_registers_size (_esoc_registers - _soc_registers)
+
extern u8 _framebuffer[];
extern u8 _eframebuffer[];
#define _framebuffer_size (_eframebuffer - _framebuffer)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index edf9c41493..a0b48b2e6d 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,6 +29,8 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00200000, 512K)
RAMSTAGE(0x00280000, 128K)
+ /* 0x18100000 -> 0x18540000 */
+ SOC_REGISTERS(0x18100000, 0x440000)
/*
* GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock
* and then through the identity mapping in ROM stage.